1. Field of the Invention
This invention relates in general to the field of information storage, and more particularly to the acquisition of timing signals in a read channel.
2. Description of the Related Art
Many systems using digital data need to convert an analog signal to digital data for further use. Converting analog data to digital data may require a clock synchronized with the analog data.
Often, in data communication or transmission systems, data is formatted with timing information which may be retrieved in order to establish a clock that has the same frequency and phase offset as the data. The schematic block diagram shown in FIG. 1 is one way in which the clock may be synchronized with the data. ADC 101 receives a signal from the transducing head and a clock signal from interpolator 103 for converting the analog signal from the transducing head to a digital signal. The ADC 101 provides a signal to the timing loop control 102, which in turn provides an adjusted clock to the interpolator 103.
FIG. 2 shows one schematic representation of the interpolator 103. The adjusted clock, CLK A, provides an input to a phase delay circuit 201 wherein a second clock, CLK B, is generated having the same frequency as CLK A but with a fixed phase delay or offset of between 0 and π/2. Each CLK A and CLK B also provide inputs to a selection circuit 202, which determines when to switch from CLK A to CLK B and directs a multiplexer 203 to provide either CLK A or CLK B as the reference clock.
FIG. 3 shows the relation between CLK A and CLK B wherein the phase offset is depicted as π/2, although the phase offset may be any value between 0 and π/2. When the selection circuit switches from CLK A to CLKB, a “glitch,” which is an unwanted pulse of a short duration that interferes with the operation of process circuitry such as the ADC, may occur. The switching between CLK A and CLK B may occur at any time during either clock cycle. As a result, sometimes a glitch may occur, but sometimes not.
Looking at this phenomenon in a little more detail, the interpolator 103 provides a reference clock based upon either CLK A or CLK B. The reference clock is high when the clock from which it is based is high. For example, if the transition occurs when CLK A is low and CLK B is high, the reference clock also goes high for the remainder of the CLK B cycle, thereby generating a glitch. Likewise, if the transition occurs when CLK A is high and CLK B is low, the reference clock also goes high for the remainder of the CLK A cycle, and once again, a glitch will result. If the transition occurs when CLK A and CLK B are both either high or low, no glitch is produced. A desired reference clock signal having a transition from CLK A to CLK B does not have pulses of short duration (glitches), but instead lengthens the cycle in which the transition occurs.
Therefore, a need exists for a circuit to remove glitches from a clock signal, to improve the operational reliability of subsequent circuits which depend on a stable clock signal.